Andrii Bidochko

• Updated: June 15, 2026
• 8 min read

OpenURMA: A Clean‑Room Open Implementation of the Unified Bus Protocol

Direct Answer

OpenURMA is the first clean‑room, open‑source implementation of Huawei’s Unified Bus (UB) transport and transaction layers, delivering a radically lower‑latency, higher‑throughput alternative to traditional RDMA NICs that rely on RoCE or InfiniBand. By moving per‑application state off the NIC and exposing native CPU load/store semantics, OpenURMA cuts end‑to‑end latency for a 64‑byte remote fetch to roughly 500 ns—over four times faster than a matched OpenRoCE baseline—while consuming only about 14 % of the FPGA’s lookup tables.

Background: Why This Problem Is Hard

Modern data‑center workloads—large‑scale AI training, real‑time inference pipelines, and high‑frequency trading—depend on Remote Direct Memory Access (RDMA) to move data with minimal CPU involvement. In practice, however, the performance ceiling is not the physical network but the network interface card (NIC) itself. Conventional RDMA stacks such as RoCE (RDMA over Converged Ethernet) and InfiniBand inherit the “Queue Pair” abstraction, which forces the NIC to maintain a full set of connection state for every (application, remote endpoint) pair. When a server runs thousands of concurrent AI services, this per‑connection bookkeeping balloons to hundreds of megabytes of on‑card memory.

Beyond memory pressure, the Queue Pair model mandates a four‑traversal PCIe round‑trip for a 64‑byte operation. Each traversal adds tens of nanoseconds, inflating the overall latency by an order of magnitude relative to the raw wire speed. The result is a paradox: the network is capable of sub‑microsecond delivery, yet the NIC’s software‑defined path throttles the system to several microseconds, eroding the benefits of low‑latency AI inference and distributed training.

Attempts to mitigate these bottlenecks—such as NIC off‑load engines, larger PCIe lanes, or aggressive caching—only address symptoms. They cannot fundamentally change the underlying abstraction that couples per‑application state to the transport layer, nor can they eliminate the PCIe traversal overhead without redesigning the protocol stack.

What the Researchers Propose

The paper introduces OpenURMA, an open, clean‑room implementation of the Unified Bus (UB) specification, a public 2025 standard originally shipped in Huawei’s Ascend 950 silicon. UB re‑architects the RDMA abstraction in two key ways:

• State Decoupling: Per‑application endpoint metadata is separated from per‑host transport context. This means that adding a new application only grows the connection state linearly, not multiplicatively, dramatically reducing on‑card memory requirements.
• Native Load/Store Path: Remote memory is accessed via CPU load/store instructions that target an on‑chip bus controller, bypassing the PCIe‑bound Queue Pair traversal entirely. Ordering guarantees become optional (opt‑in), allowing latency‑critical paths to proceed without unnecessary serialization.

OpenURMA materializes this specification across three implementation tiers:

1. Synthesisable RTL on Xilinx Alveo U50, demonstrating that the protocol can be realized in hardware with modest resource usage.
2. Cycle‑level SystemC simulator modeling a two‑node system, enabling precise performance analysis without physical hardware.
3. gem5 full‑system scaffold that integrates the UB transport with a conventional Linux stack, providing a realistic baseline for comparison against OpenRoCE (RoCEv2 RC).

By delivering a matched, open‑source baseline, the researchers can quantify the exact latency and throughput gains that the UB abstraction offers—something closed‑source silicon cannot disclose.

How It Works in Practice

The OpenURMA workflow can be broken down into four conceptual stages:

1. Connection Initialization

When an application registers a remote endpoint, it creates a lightweight endpoint descriptor that lives in host memory. The UB transport layer on the host maps this descriptor to a global transport context that is shared across all applications on the node. Because the transport context is independent of the number of endpoints, scaling to thousands of services incurs only a linear increase in memory.

2. Transaction Issuance

To read remote memory, the application issues a standard CPU load instruction targeting a special address range mapped to the UB bus controller. The controller translates this request into a network packet, appends the necessary routing headers, and forwards it over the data‑center fabric.

3. Remote Execution

The remote host’s UB controller receives the packet, performs the requested load/store directly against its local memory, and returns the result in a response packet. Since the operation is a pure memory access, no kernel mediation or DMA setup is required, eliminating the typical PCIe round‑trip.

4. Completion and Ordering

Responses are delivered back to the originating CPU’s load/store pipeline. If the application requires strict ordering (e.g., for consistency guarantees), it can enable the optional ordering mode; otherwise, the path remains fully asynchronous, allowing maximum parallelism.

What distinguishes OpenURMA from traditional RDMA stacks is this seamless integration of remote memory operations into the CPU’s native instruction stream. The hardware implementation on the Alveo U50 acts as a thin “bus bridge,” translating load/store semantics to network messages without the heavyweight Queue Pair machinery.

Evaluation & Results

The authors evaluated OpenURMA against a rigorously matched OpenRoCE baseline across three environments: the RTL prototype on the U50, the SystemC simulator, and the gem5 full‑system model. The primary benchmark was a 64‑byte remote fetch, a canonical micro‑operation that stresses latency more than bandwidth.

Test Scenarios

• Single‑hop latency: Measure the round‑trip time for a solitary 64‑byte load.
• Throughput scaling: Issue concurrent loads from 1 to 1024 parallel streams to assess how the system handles fan‑out.
• Resource utilization: Record FPGA LUT consumption and power draw to gauge implementation efficiency.

Key Findings

• OpenURMA achieved an end‑to‑end latency of ~500 ns for the 64‑byte fetch, which is 4.37× faster than the OpenRoCE baseline (≈ 2186 ns).
• Throughput under high fan‑out was 2.80× higher, demonstrating that the load/store path scales linearly with concurrent streams.
• The RTL implementation occupied only ≈ 14 % of the U50’s lookup tables, leaving ample headroom for additional logic such as security checks or compression.
• Power measurements indicated a modest increase (< 5 %) over the baseline, confirming that the latency gains do not come at a prohibitive energy cost.

These results collectively validate the UB hypothesis: decoupling state and exposing native load/store semantics can dramatically improve RDMA performance without sacrificing resource efficiency.

Why This Matters for AI Systems and Agents

AI workloads are increasingly distributed across clusters of GPUs, TPUs, and specialized accelerators. The speed at which model parameters, embeddings, or intermediate tensors can be fetched from remote memory directly influences training convergence time and inference latency. OpenURMA’s sub‑microsecond remote fetch capability unlocks several practical benefits:

• Faster Model Parallelism: When large language models are split across nodes, each shard frequently accesses parameters residing on peers. Reducing fetch latency from microseconds to sub‑microseconds can shave seconds off epoch times at scale.
• Real‑time Agent Coordination: Multi‑agent reinforcement learning often requires rapid state sharing. OpenURMA’s low‑latency path enables tighter synchronization loops, improving policy convergence.
• Edge‑to‑Cloud Offload: AI agents running on edge devices can pull inference data from a central memory pool without incurring the PCIe overhead that would otherwise dominate the latency budget.
• Cost‑Effective Scaling: Because the UB implementation uses a fraction of FPGA resources, data‑center operators can pack more functionality per accelerator board, reducing hardware spend.

For organizations building AI‑driven products, these gains translate into higher throughput, lower latency SLAs, and a competitive edge in latency‑sensitive markets such as finance, autonomous systems, and interactive AI assistants.

Developers looking to integrate OpenURMA‑style capabilities into their stacks can explore existing UB‑based tooling. For example, the Telegram integration on UBOS demonstrates how low‑latency messaging can be combined with AI agents, while the OpenAI ChatGPT integration showcases seamless remote memory access for large language model serving.

What Comes Next

While OpenURMA marks a significant step forward, several open challenges remain:

• Security and Isolation: Native load/store semantics bypass traditional NIC‑level protection. Future work must embed fine‑grained access control and encryption within the UB controller.
• Multi‑Tenant Environments: Scaling the decoupled state model to cloud‑scale multi‑tenant clusters will require robust namespace management and QoS enforcement.
• Standardization and Ecosystem Adoption: Although UB is a public specification, broader industry endorsement is needed. Open‑source driver stacks, compiler support, and integration with popular AI frameworks (e.g., PyTorch, TensorFlow) will accelerate adoption.
• Hardware Diversification: Porting the RTL design to ASICs or other FPGA families could further reduce power and latency, opening doors for edge deployments.

Potential application domains extend beyond AI. High‑frequency trading platforms could exploit sub‑microsecond remote reads for order book updates, while scientific simulations could benefit from faster halo exchanges in distributed PDE solvers.

Organizations interested in experimenting with UB‑based workflows can start with the UBOS platform overview, which provides a sandbox for building custom agents and pipelines. For startups seeking rapid prototyping, the UBOS for startups page outlines pricing and support options.

Looking ahead, the research community is poised to explore hybrid models that combine UB’s low‑latency path with traditional RDMA’s mature ecosystem, delivering a flexible stack that can be tuned per workload.

References

OpenURMA: A Clean‑Room Open Implementation of the Unified Bus Protocol (arXiv:2605.28717v1)

Andrii Bidochko

CTO UBOS

Andrii Bidochko is an AI entrepreneur and researcher focused on AI agents, reinforcement learning, and autonomous systems. He writes about the technologies shaping the future of machine intelligence, from frontier models and agent architectures to real-world AI applications.