- Updated: March 3, 2026
- 13 min read
Intel Unveils 288‑Core Xeon CPU on 18A Process Node – A Data‑Center Game‑Changer
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Intel aims its Xeon 6+ ‘Clearwater Forest’ processors primarily for telecom, cloud, and edge AI workloads as they feature Advanced Matrix Extensions (AMX), QuickAssist Technology (QAT), and Intel vRAN Boost technologies.Go deeper with TH Premium: CPU (Image credit: Tom’s Hardware)CPU scaling with DLSSRyzen to the top: How AMD innovated in the gaming CPU marketHow ARM is working its way into PCsAMD CES 2026 gaming trends press Q&A roundtable transcriptIntel’s Xeon 6+ processors with up to 288 cores combine 12 compute chiplets containing 24 energy-efficient Darkmont cores per tile that are produced using 18A manufacturing technology, two I/O tiles made on Intel 7 production node, as well as three active base tiles made on Intel 3 fabrication process. The compute tiles are stacked on top of the base dies using Intel’s Foveros Direct 3D technology, whereas lateral connections are enabled by Intel’s EMIB bridges.Image 1 of 2(Image credit: Intel)(Image credit: Intel)Intel’s ‘Darkmont’ efficiency cores have received rather meaningful microarchitectural upgrades. Each core integrates a 64 KB L1 instruction cache, a broader fetch and decode pipeline, and a deeper out-of-order engine capable of tracking more in-flight operations.The number of execution ports has also been increased in a bid to improve both scalar and vector throughput under heavily threaded server workloads. You may like Benchmarks of Performance-core only Bartlett Lake CPU emerge Intel Bartlett Lake-S CPUs reportedly wield 12 blazing P-cores and 5.8 GHz boost Intel returns to boxed workstation CPUs with Xeon 600 — Granite Rapids WS delivers up to 86 cores, 4TB of memory, and 128 PCIe 5 lanes From a cache hierarchy standpoint, the design groups cores into four-core blocks that share approximately 4 MB of L2 cache per block. As a result, the aggregate last-level cache across the full package surpasses 1 GB, roughly 1,152 MB in total.This unusually large pool is intended to keep data close to hundreds of active cores and reduce dependence on external memory bandwidth, which in turn is meant to both increase performance and lower power consumption.Platform-wise, the processor remains drop-in compatible with the current Xeon server socket, so the CPU has 12 memory channels that support DDR5-8000, 96 PCIe 5.0 lanes with 64 lanes supporting CXL 2.0.(Image credit: Intel)Intel positions Clearwater Forest for telecom and cloud workloads. The company says operators deploying 5G Advanced and future 6G networks increasingly rely on server CPUs for virtualized RAN and edge AI inference, as they do not want to re-architect their data centers in a bid to accommodate AI accelerators.By combining matrix/vector acceleration, vRAN offloads (using the vRAN Boost), large caches, and broad I/O in one platform, the CPU can perform jobs that are normally reserved for various accelerators that consume more power and take up space.Also, extreme core count of Xeon 6+ ‘Clearwater Forest’ CPUs — that approaches 288 cores for uniprocessor configurations and 576 cores in dual socket configurations, enabling a single server to host dozens or even hundreds of virtual machines while maintaining power efficiency and low latency.Stay On the Cutting Edge: Get the Tom’s Hardware NewsletterGet Tom’s Hardware’s best news and in-depth reviews, straight to your inbox.Contact me with news and offers from other Future brandsReceive email from us on behalf of our trusted partners or sponsorsSystems based on Intel’s Xeon 6+ processors will be available later this year. Follow Tom’s Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds. TOPICS Intel Xeon See all comments (13) Anton ShilovSocial Links NavigationContributing WriterAnton Shilov is a contributing writer at Tom’s Hardware.Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. Read more Benchmarks of Performance-core only Bartlett Lake CPU emerge Intel Bartlett Lake-S CPUs reportedly wield 12 blazing P-cores and 5.8 GHz boost Intel returns to boxed workstation CPUs with Xeon 600 — Granite Rapids WS delivers up to 86 cores, 4TB of memory, and 128 PCIe 5 lanes Intel’s upcoming Core Ultra 9 mobile CPU outperforms most desktop counterparts in new benchmark Amazon unveils 192-core Graviton5 CPU with massive 180 MB L3 cache in tow Intel displays tech to build extreme multi-chiplet packages 12 times the size of the largest AI processors, beating TSMC’s biggest Latest in CPUs Intel Chairman Frank Yeary retires, Craig Barrat to become the new chairman of the Board of Directors AMD details Ryzen AI 400 desktop with up to 8 cores, Radeon 860M graphics Intel mobile CPUs have achieved up to 95x performance uplift over the past two decades AMD’s K6-III ‘Sharptooth’ debuted this week in 1999 with on-die L2 cache to savage the Intel Pentium II Behind the scenes of our massive CPU retest for Bench — testing at 1080p, choosing new apps, and gathering data for a decade of CPUs Testing CPU scaling in Resident Evil Requiem Latest in News Seagate begins shipping 44TB hard drives with HAMR tech to data centers AI memory crunch forces DRAM market into ‘hourly pricing’ model, report claims Intel’s make-or-break 18A process node debuts for data center with 288-core Xeon 6+ CPU Nvidia RTX 5070 mobile GPU looks set to get more VRAM despite global memory crisis Apple’s new MacBook Air gets M5 and doubles starting storage Drones attack several AWS Middle East region data centers amid Iran war, leading to outages 13 Comments Comment from the forums Last things first: The article said:Systems based on Intel’s Xeon 6+ processors will be available later this year. Okay, so not a launch, but rather just a formal announcement. The article said:From a cache hierarchy standpoint, the design groups cores into four-core blocks that share approximately 4 MB of L2 cache per block. As a result, the aggregate last-level cache across the full package surpasses 1 GB”as a result” ? No, 4 MB per 4 cores = 1 MB per core. So, the total amount of L2 cache is just 288 MB.I have seen where it has 1152 of last level cache, but the way it’s written makes it sound like you’re just talking about L2. The article said:Intel aims its Xeon 6+ ‘Clearwater Forest’ processors primarily for telecom, cloud, and edge AI workloads as they feature Advanced Matrix Extensions (AMX)Wait, this has AMX? Or, is it just the Diamond Rapids members of the family that would have that?I’d be rather surprised if Clearwater Forest has AMX, since that adds a non-trivial amount of die area per core. Also, what about AVX-512? Reply So, reviewing what they’ve previously disclosed about, I see that mentions of AMX, AVX-512, and AVX10 are conspicuously absent. https://www.tomshardware.com/desktops/servers/intel-reveals-288-core-xeon Another downside is that it’s still PCIe 5.0-based (and CXL 2.0).By contrast, AMD’s Venice, probably launching around the same time, is moving up to PCIe 6.0 / CXL 3.0. Here are some other juicy tidbits, from the above article (17% IPC boost on SPECint!): Reply Funny how that piece of exciting news is so utterly boring to me, not just as a consumer, but also as a former technical architect.The scale you need to make these worth having is so far beyond anything a technically minded individual might be responsible for, it can really only appeal to bean-counters, or perhaps a very abstract mind. I’ve thrived on hands-on and the confidence I had after trying to break things. Breaking these would be way above my pay grade, so you’d have to use blind faith. That turns to cause bigger messes, not guarantee fewer.Reply bit_user said:So, reviewing what they’ve previously disclosed about, I see that mentions of AMX, AVX-512, and AVX10 are conspicuously absent.These aren’t meant to replace P-core Xeons, but front-end ARMs. I’d have been surprised to see AMX there, not even sure there is much of any floating-point in front-ends.Quite honestly it’s the kind of workload I’d have expected to move into network ASICs as IP blocks, but that’s a hosting customer decision and I’m not sure which hyperscalers expose programmable fabrics today to customers. Reply I am a bit sceptic when it comes to this giagantism. On one hand, even chips much bigger are likely to never catch everyones scale-up requirements, so scale-out needs to be part of the design anyway.When you do scale-out, putting more eggs in a basket creates a conflict between the cost of consolidation vs the cost of administering more instances. Finding that sweet spot won’t be easy and you may need to maintain that across several generations outside a physical server, since complete slash-and burn or green-field deployments aren’t normal beyond the 1st build-out. Well good thing, that’s no longer my job!Reply abufrejoval said:These aren’t meant to replace P-core Xeons, but front-end ARMs.The article pretty clearly indicated they had it, which is why I was searching for confirmation. abufrejoval said:not even sure there is much of any floating-point in front-ends.Yes, there very much is! Vector/FP is the area where Skymont improved the most over Crestmont/Gracemont, and even those had AVX2. Reply abufrejoval said:I am a bit sceptic when it comes to this giagantism.On one hand, even chips much bigger are likely to never catch everyones scale-up requirements, so scale-out needs to be part of the design anyway.I think that’s why mainstream servers have only 2 sockets. The main benefit of more cores/server is that you get higher density and it requires less infrastructure per core. That seems to be the main argument behind scaling up core counts per (server) CPU. Reply Darkmont, based on slides, appears to be identical to Skymont for the most part.Seems like maybe some additional math instruction. Videocardz has the slide deck: https://videocardz.com/newz/intel-announces-xeon-6-clearwater-forest-at-mwc-2026-core-200k-likely-the-next-plus Reply thestryker said:Darkmont, based on slides, appears to be identical to Skymont for the most part. Seems like maybe some additional math instruction.Oh, good point. I see now that Skymont also has a 416-entry OoO window, so they must’ve been comparing Darkmont to Gracemont.Chips & Cheese’s Skymont details also align with the Darkmont slide’s claims about increases in load & store AGUs. https://chipsandcheese.com/p/skymont-intels-e-cores-reach-for-the-sky Reply bit_user said:The main benefit of more cores/server is that you get higher density and it requires less infrastructure per core. That seems to be the main argument behind scaling up core counts per (server) CPU.These are as close to perfect as it gets for communications edge which is probably why the MWC announcement. Between the density and accelerators I’d imagine these will be hard to beat outside of bespoke solutions. Reply View All 13 Comments Show more comments
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Andrii Bidochko is an AI entrepreneur and researcher focused on AI agents, reinforcement learning, and autonomous systems. He writes about the technologies shaping the future of machine intelligence, from frontier models and agent architectures to real-world AI applications.